A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having MOS transistors with stress applying mechanisms and its manufacture method. A field effect transistor having a gate electrode made of a lamination of a gate insulating film and a conductor film formed on a semiconductor active region is called a MOS transistor.
B) Description of the Related Art
Micro patterning has advanced in order to improve the integration density and operation speed of a silicon semiconductor integrated circuit. Micro patterning shortens the gate length of a MOS transistor. At a gate length of 65 nm or shorter, there is a limit on performance improvement by micro patterning.
As technologies of improving the performance of a MOS transistor apart from micro patterning, attention has been paid to a stress transistor which improves the mobility of carriers by strain (stress application). Strain is generated by applying a stress to the channel region of a MOS transistor to increase the mobility of electrons or holes and improve an on-current.
The mobility of electrons of an n-channel (N) MOS transistor is improved by tensile stress along the gate length direction. The mobility of holes of a p-channel (P) MOS transistor is improved by compressive stress along the gate length direction.
If the source/drain regions of an NMOS transistor is made of an epitaxial crystal layer of silicon-carbon (Si—C) mixed crystal (C-doped Si) having a smaller lattice constant than that of a Si substrate, a tensile stress is applied to Si crystal in the channel so that the mobility of electrons is increased (refer to K. Ang et al.: IEDM Tech. Dig., 2004, p. 1069).
If the source/drain regions of a PMOS transistor is made of an epitaxial crystal layer of silicon-germanium (Si—Ge) mixed crystal having a larger lattice constant than that of a Si substrate, a compressive stress is applied to Si crystal in the channel so that the mobility of holes is increased (refer to T. Ghani et al.: IEDM Tech. Dig., 2003, p. 978 and Y. S. Kim et al.: Proceedings of ESSDERC 2005. p. 305)
As the gate length is shortened further, it becomes more difficult to realize a shallow junction depth of the source/drain regions to suppress the short channel effect. It has been proposed to selectively grow Si epitaxial layers on Si substrate, and form extension regions and source/drain regions in or through the epitaxial layers (refer to Wakabayashi et al.: IEDM 2005, pp. 151-154).
By applying stress to the channel of a MOS transistor, it becomes possible to increase the mobility of carriers and improve the performance of the MOS transistor. The mobility of electrons of an NMOS transistor is increased by tensile stress, and the mobility of holes of a PMOS transistor is increased by compressive stress.